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HEI_FG_model
retention_FG
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README.md

Verilog-A model of FG transistor

Floating Gate Transistor Verilog-A Modeling in Cadence:

This Verilog-A model simulates the behavior of a floating gate (FG) transistor with injection modeling and short-term retention. The code includes calculations for tunneling, capacitive coupling, and injection current updates, enabling accurate simulations of FG transistor dynamics.

Model Description The model calculates the floating gate voltage (Vfg) based on the contributions of various capacitances and voltages at the terminals. It includes:

• Injection current modeling (Iinj) for charge addition to the FG.

• Capacitance modeling based on device dimensions and oxide parameters.

• Threshold voltage (Vtp) and floating gate voltage updates (delta_Vfg) influenced by injection dynamics.

• Drain current (Id) calculated using the EKV model principles.

Prerequisites

• Cadence Virtuoso environment with AMS Designer or Spectre simulator installed. • Access to required dependencies: constants.vams and disciplines.vams. • Model files for parameter initialization (deltavt.csv, vtp.csv, etc.).

Model Files

Verilog-A File

• HEI_FG_model.va: Contains the Verilog-A code for the FG transistor model.

Initialization Files

• deltavt.csv: Contains the initial delta_Vfg values.

• vtp.csv: Contains the initial threshold voltage (Vtp) values.

Output Files

• IS.csv: Logs the simulated source current (Id).

• Iinj.csv: Logs the injection current (Iinj) for each simulation step.

• deltavt.csv: Updates the floating gate voltage delta (delta_Vfg).

• vtp.csv: Updates the threshold voltage (Vtp).

How to Use

Step 1: Set Up Model Files

  1. Copy the Verilog-A model file (HEI_FG_model.va) to your Cadence project directory.

  2. Ensure that deltavt.csv and vtp.csv files are placed in the specified file paths mentioned in the Verilog-A code. Update file paths in the code if necessary.

Step 2: Add Model to Cadence

  1. Open Cadence Virtuoso.

  2. In the Library Manager, create a new cell for the FG transistor model.

  3. Import the Verilog-A code into the new cell. o Go to File > Import > Verilog-A, then select HEI_FG_model.va.

  4. Compile the model to ensure there are no syntax errors.

Step 3: Include in Simulation

  1. Add the FG transistor model as a component in your schematic. o Assign the d, g, s, b terminals to the drain, gate, source, and bulk of the transistor.
  2. Set simulation parameters such as supply voltages and simulation time.
  3. Include the .csv initialization files as required.

Step 4: Run Simulation

  1. Use the Spectre or AMS simulator to run transient or DC simulations.
  2. Observe the output files (IS.csv, Iinj.csv, etc.) for logged results. o IS.csv: Source current over time. o Iinj.csv: Injection current values. o deltavt.csv: Updated floating gate voltage changes.

Step 5: Analyze Results

  1. Use plotting tools in Cadence to visualize node voltages and currents.
  2. Evaluate the injection dynamics and the effect on Vfg, Id, and other parameters.

Key Parameters • W, L: Transistor dimensions (channel width and length). • Vfg0: Initial floating gate voltage. • Vtp: Threshold voltage. • delta_t: Injection pulse width • Iinj0, V_inj: Constants governing the injection current behavior.

Notes • Ensure all file paths in the Verilog-A code match your project directory. • Modify parameters (e.g., dimensions, oxide thickness) to suit your specific FG transistor design. • Use appropriate time step (delta_t) and simulation duration to capture FG dynamics accurately.

Retention Modeling of Floating Gate (FG) Transistor

This Verilog-A model captures the short-term retention behavior of a Floating Gate (FG) transistor. It models the decay or change in the floating gate voltage (Vfg) due to tunneling currents over time and outputs the updated voltage (vt_changed_out).

Model Overview The retention model computes:

  1. Leakage Current (IL): Determined by gate tunneling current mechanisms and device parameters.
  2. Voltage Drift (vt_1): Represents the decay of the floating gate voltage over time due to charge leakage.
  3. Observable Voltage (vt_changed_out): The retained voltage after accounting for leakage, allowing for simulation of retention dynamics in FG-based circuits.

The model calculates these values based on physical constants, material properties, and geometric dimensions of the FG device.

Key Features

• Models gate leakage current due to tunneling and its effect on short-term retention. • Accounts for capacitance contributions of the device structure. • Provides real-time updates of retained voltage (vt_changed_out). • Outputs retention data (vt_1) for analysis and evaluation.

Files Verilog-A Model

• retention_FG.va: Contains the Verilog-A implementation of the retention model. Output Files

• retention.csv: Logs the intermediate voltage (vt_1) over simulation time.

How to Use

Step 1: Setup

  1. Copy the retention_FG.va file to your Cadence project directory.
  2. Ensure that file paths for retention.csv are correct or update them to match your directory structure.

Step 2: Add Model in Cadence

  1. Create a new cell in Cadence for the retention model.
  2. Import the Verilog-A model (retention_FG.va) into the cell.
  3. Compile the model to ensure there are no syntax errors.

Step 3: Schematic Integration

  1. Add the model as a component to your Cadence schematic.
  2. Connect the output node vt_changed_out to observe the retention dynamics.
  3. Set up simulation parameters, including transient simulation for sufficient time to observe retention.

Step 4: Run Simulation

  1. Use Spectre or AMS simulator to run the simulation.
  2. Observe the results for the vt_changed_out node and analyze the retention.csv file for intermediate data (vt_1).

Model Parameters

• Device Geometry o W, L: Gate transistor width and length. o Wtun, Ltun: Tunneling region dimensions. o Wdirect, Ldirect: Direct transistor dimensions.

• Material Properties o toxe: Oxide thickness. o epsrox: Oxide relative permittivity. o Ut: Thermal voltage.

• Constants o fi_b: Barrier height for tunneling. o meff: Effective mass of tunneling carriers. o J: Tunneling current density.

Outputs

  1. vt_changed_out o The updated voltage after considering gate leakage current effects. o Represents the retained voltage on the floating gate over time.
  2. retention.csv o Logs the calculated drift voltage (vt_1) at each simulation step.

Authors and acknowledgment

• Sayma Nowshin Chowdhury • Matthew Chen • Sahil Shah

License

Copyright (c) [2024] [Sayma Nowshin Chowdhury, Matthew Chen, Sahil Shah]

All rights reserved.

Permission to Use

The user is permitted to use, copy, and modify this software for academic and non-commercial research purposes, provided the following conditions are met:

  1. Attribution: Any publication, presentation, or software that uses or is derived from this code must include a citation to the following paper: Citation:

Sayma Nowshin Chowdhury, Matthew Chen, Sahil Shah, "Analysis and Verilog-A Modeling of Floating-Gate Transistors". IEEE Open Journal of Circuits and Systems.

  1. Redistribution: Redistribution of this software, in its original or modified form, is only permitted under this license, provided that the following conditions are met: o This LICENSE file must be included with any redistributed versions. o Acknowledge the original author(s) in any derivative works.

Disclaimer This model is provided for academic and educational purposes only. The authors and contributors shall not be held liable for any damage resulting from the use of or inability to use this software.